A Verilog HDL function cannot drive more than one output, can not contain delays.

The functions are normally used to modle:
Mathematical Manipulation
Combinational Logic Sequences
Conversions of Data
		
The following are some of the general rules for functions:
   - Functions must contain at least one input argument.
   - Functions cannot contain an inout or output declaration.
   - Functions cannot contain time controlled statements (#, @, wait).
   - Functions must contain a statement that assigns the return value to the implicit function name register.

Syntax:

  function [msb:lsb] function_name;
    input [msb:lsb] input_arguments;
    reg [msb:lsb] reg_variable_list;
    parameter [msb:lsb] parameter_list;
    
             ... statements ...

  endfunction


module myparity (addr, parity);

input [7:0]  addr;
output        parity;
reg           parity;

always@(addr)
begin
  parity = calc_parity(addr);
end

function calc_parity;
input [7:0] address;

begin
  calc_parity = ^address;
end
endfunction

endmodule