`timescale 1ns / 1ns
module test_xor;

reg  a, b;
wire  f;

xor  uut ( f, a, b);

initial begin
         a = 0;  b= 0;
  #10 a =0; b = 1;
  #10 a =1; b = 0;
  #10 a =1; b = 1;
  #10 $stop;
end

initial $monitor($time, "ns, a=%b, b=%b, f=%b", a, b, f);

endmodule