module  dff_e1 ( clk, d, q);

input  clk, d;
output q;

reg    q;

always @ ( posedge clk )
begin
  q <= d;
end

endmodule


`timescale 1ns/1ns
module  dff_e1_tb;

reg    clk, d;
wire   q;

dff_e1  uut( clk, d, q);


always  #10 clk = ~ clk;

initial
begin
  clk = 0;
  d = 1;
 #5 d  = 0;
 #20 d = 1;
 #20 d = 0;
 #15  $stop;
end



endmodule