module  dff_e2 ( clk, rst, d, q);

input  clk, d, rst;
output q;

reg    q;

always @ ( posedge clk or posedge rst)
begin
  if(rst ) 
       q <= 0;
  else  
       q <= d;
end

endmodule


`timescale 1ns/1ns
module  dff_e2_tb;

reg    clk, rst, d;
wire   q;

dff_e1  uut( clk, rst, d, q);



always  #10 clk = ~ clk;

initial
begin
  clk = 0;
  rst = 1;
  d = 1;
 #6 rst = 0;
 #5 d  = 0;
 #20 d = 1;
 #20 d = 0;
 #15  $stop;
end



endmodule