module  dff_e3 ( clk, rst, d, q);

input  clk,  rst;
input [3:0] d;
output [3:0] q;

reg   [3:0] q;

always @ ( posedge clk or posedge rst)
begin
  if(rst ) 
       q <= 0;       
  else  
       q <= d;
end

endmodule


`timescale 1ns/1ns
module  dff_e3_tb;

reg    clk, rst;
reg [3:0] d;
wire [3:0] q;

dff_e1  uut( clk, rst, d, q);


always  #10 clk = ~ clk;

initial
begin
  clk = 0;
  rst = 1;
  d = 4'b1100;
 #6 rst = 0;
 #5 d  = 8;
 #20 d = 10;
 #20 d = 4;
 #15  $stop;
end



endmodule