LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY bcd IS
PORT
(
  clk : IN STD_LOGIC;
  dout: OUT STD_LOGIC_VECTOR(3 downto 0) );
END bcd;

ARCHITECTURE design OF bcd IS

SIGNAL tmp: STD_LOGIC_VECTOR(3 downto 0);

BEGIN

PROCESS (clk )
BEGIN
  if (rising_edge(clk)) then
    if (tmp = 9) then
    -- if (tmp = "1001") then
         tmp <= (others=>‘0’);
      -- tmp <= "0000";
    else
        tmp <= tmp + 1;
    end if;
end if;
END PROCESS;
dout <= tmp;

END design;