LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clkdiv8 is
port(clk1 : in std_logic;
  clk2 : out std_logic);
end clkdiv8;

architecture beh of clkdiv8 is
signal counter: std_logic_vector(2 downto 0);
begin

   process (clk1)
   begin
     if (rising_edge(clk1)) then
        if (counter=7) then
            clk2 <= '1';
            counter <= (others=>’0’);
        elsif(counter<3) then
            clk2 <= '1';
            counter <= counter + 1;
        else
            clk2 <= '0';
            counter <= counter + 1;
        end if;
     end if;
     end process;

end beh;