Library ieee;
Use ieee.std_logic_1164.all;
Entity dff is
Port ( d, clk: in std_logic;
  q: out std_logic );
End dff;

Architecture beh of dff is
begin

process( clk )
begin
  if (clk'event and clk = '1') then
    -- if (rising_edge (clk) ) then
    -- if (falling_edge (clk) ) then
     q <= d;

  end if;
end process;

End beh;


--------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY dff_tb IS
END dff_tb;

ARCHITECTURE beh OF dff_tb IS

component dff
PORT (
  d, clk : IN STD_LOGIC;
  q : OUT STD_LOGIC
);
end component;
signal d, clk, q : STD_LOGIC;

BEGIN

uut: dff port map (
  d => d,
  clk => clk,
  q => q
);

Process
Begin
  Clk <= '0';
  Wait for 10 ns;
  Clk <= '1';
  Wait for 10 ns;
End process;

Process
Begin
  d <='0';
  Wait for 8 ns;
  d <='1';
  Wait for 20 ns;
  d <='0';
  Wait for 8 ns;
  Wait;
End process;

END beh;