LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity down_counter is
port(clk, load : in std_logic;
 din : in std_logic_vector(3 downto 0);
 cnt : out std_logic_vector(3 downto 0));
end down_counter;

architecture arch of down_counter is
signal tmp: std_logic_vector(3 downto 0);
begin

process (clk, load)
begin
  if (load='1') then
      tmp <= din;
   elsif (rising_edge(clk)) then
      tmp <= tmp - 1;
   end if;
end process;
cnt <= tmp;

end arch;