LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY mealyfsm IS
PORT
(
  reset, a, clk : IN STD_LOGIC;
  y: OUT STD_LOGIC
);

END mealyfsm;


ARCHITECTURE beh OF mealyfsm IS

type state_type is (S0, S1);
signal cs, ns: state_type;

Begin
  Process(reset, clk)
  Begin
    If(reset='1') then
        cs <= S0;
    elsif (rising_edge(clk)) then
        cs <= ns;
    end if;
  end process;


  Process(cs, a)
  Begin
  Case (cs) is
    When S0 =>
       If (a='1') then
         ns <= S1; y <= '1';
       else
         ns <= S0; y <= '0';
       end if;

    When S1 =>
        If (a='1') then
          ns <= S1; y <= '0';
        else
          ns <= S0; y <= '1';
        end if;

    When others=> y<= '0'; ns <= S0;
   end case;

   end process;

END beh;

---------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY mealyfsm_tb IS
END mealyfsm_tb;

ARCHITECTURE beh OF mealyfsm_tb IS

component mealyfsm
PORT
(
  reset, a, clk : IN STD_LOGIC;
  y: OUT STD_LOGIC
);
end component;

signal reset, a, clk : STD_LOGIC;
signal y: STD_LOGIC;

BEGIN

Uut: mealyfsm port map (
  reset => reset,
  a => a,
  clk => clk,
  y => y
);

reset <= '1', '0' after 5 ns, '0' after 100 ns;

process
begin
clk<= '0'; wait for 10 ns;
clk<= '1'; wait for 10 ns;
end process;

a<= '0', '1' after 12 ns, '0' after 54 ns, '1' after 70 ns;

END beh;