LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY moorefsm IS
PORT
(
  reset, a, clk : IN STD_LOGIC;
  y: OUT STD_LOGIC
);
END moorefsm;

ARCHITECTURE beh OF moorefsm IS
type state_type is (S0, S1);
signal cs, ns: state_type;

BEGIN

Process(reset, clk)
Begin
If (reset = '1') then
  cs <= S0;
elsif (rising_edge(clk)) then
  cs <= ns;
end if;
End process;

Process(cs, a)
Begin
  case (cs) is
  When S0 => y <= '0';
     If (a='1') then
       ns <= S1;
     else
       ns <= S0;
     end if;
  
  When S1 => y <= '1';
     If (a='1') then
       ns <= S1;
     else
       ns <= S0;
     end if;

  When others=> y<= '0'; ns <= S0;
  end case;

end process;

END beh;

----------------------------------------------------------


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY moorefsm_tb IS
END moorefsm_tb;

ARCHITECTURE beh OF moorefsm_tb IS

component moorefsm
PORT
(
  reset, a, clk : IN STD_LOGIC;
  y: OUT STD_LOGIC
);
end component;

signal reset, a, clk : STD_LOGIC;
signal y: STD_LOGIC;

BEGIN

Uut: moorefsm port map (
  reset => reset,
  a => a,
  clk => clk,
  y => y
);

reset <= '1', '0' after 5 ns, '0' after 100 ns;

clk<= '0', '1' after 10 ns, '0' after 20 ns ,
'0' after 30 ns, '1' after 40 ns,
'0' after 50 ns, '1' after 60 ns,
'0' after 70 ns, '1' after 80 ns,
'0' after 90 ns, '1' after 100 ns;

a <= '0', '1' after 12 ns, '0' after 56 ns;

END beh;