-- myand.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY myand IS
PORT
(
  A, B : IN STD_LOGIC;
  C : OUT STD_LOGIC
);
END myand;

ARCHITECTURE dataflow OF myand IS
BEGIN
   C <= A and B;
END dataflow;




LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY myand_tb IS
END myand_tb;

ARCHITECTURE beh OF myand_tb IS
component myand
PORT
(
  A, B : IN STD_LOGIC;
  C : OUT STD_LOGIC
);
end component;

signal TA, TB : STD_LOGIC;
signal TC: STD_LOGIC;


BEGIN
uut: myand port map (
  A => TA,
  B => TB,
  C => TC
);

Process
Begin
  TA <='0'; TB<='0';
  Wait for 10 ns;
  TA <='0'; TB<='1';
  Wait for 10 ns;
  TA <='1'; TB<='0';
  Wait for 10 ns;
  TA <='1'; TB<='1';
  Wait for 10 ns;
  Wait;
End process;

END beh;