LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY mycir IS
PORT
(
  A, B, C, D : IN STD_LOGIC;
  F : OUT STD_LOGIC
);
END mycir;

ARCHITECTURE design OF mycir IS

signal M, N: std_logic;

BEGIN
  M <= A and B;
  N <= C and D;
  F <= M or N;
END design;






------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY mycir_tb IS
END mycir_tb;

ARCHITECTURE sim OF mycir_tb IS

component mycir
PORT
(
  A, B, C, D : IN STD_LOGIC;
  F : OUT STD_LOGIC
);
end component;

signal A, B, C, D : STD_LOGIC;
signal F: STD_LOGIC;

BEGIN

g1: mycir port map (
  A => A,
  B => B,
  C => C,
  D => D
);


Process
Begin
  A <='0'; B<='0'; C <='0'; D<='0';
  Wait for 10 ns;
  A <='0'; B<='1'; C <='0'; D<='1';
  Wait for 10 ns;
  A <='1'; B<='0'; C <='1'; D<='1';
  Wait for 10 ns;
  A <='1'; B<='1'; C <='0'; D<='0';
  Wait for 15 ns;
  A <='1'; B<='1'; C <='1'; D<='1';
  Wait for 10 ns;
  Wait;
End process;

END sim;