LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mycounter IS
PORT
(
clk : IN STD_LOGIC;
cnt : OUT STD_LOGIC_VECTOR(7 downto 0)
);
END mycounter;

ARCHITECTURE behavior OF mycounter IS
SIGNAL tmp: STD_LOGIC_VECTOR(7 downto 0);

BEGIN
PROCESS (clk )
BEGIN
if (clk' event and clk = '1') then
-- if (rising_edge(clk)) then
   tmp <= tmp + 1;
end if;
END PROCESS;
cnt <= tmp;

END behavior;