LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY fulladder IS
PORT
(
  A, B, Cin : IN STD_LOGIC;
  Cout, S : OUT STD_LOGIC
);
END fulladder;

ARCHITECTURE dataflow OF fulladder IS

signal M: std_logic;

BEGIN

  M <= A xor B;
  S <= M xor Cin;
  Cout <= ( M and Cin ) or ( A and B );

END dataflow;



--------------------------------------------------------------


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY rca4 IS
Port ( A, B: in std_logic_vector(3 downto 0);
  Cin: in std_logic;
  Cout: out std_logic;
  S: out std_logic_vector(3 downto 0));
END rca4;

ARCHITECTURE structural OF rca4 IS

component fulladder
PORT
(
  A, B, Cin : IN STD_LOGIC;
  Cout, S : OUT STD_LOGIC
);
end component;

signal CR: STD_LOGIC_VECTOR(3 downto 0);

BEGIN
U0: fulladder port map (
    A => A(0),
    B => B(0),
    Cin => Cin,
    Cout=> CR(0),
    S => S(0)
);

U1: fulladder port map (
    A => A(1),
    B => B(1),
    Cin => CR(0),
    Cout=> CR(1),
    S => S(1)
);

U2: fulladder port map (
    A => A(2),
    B => B(2),
    Cin => CR(1),
    Cout=> CR(2),
    S => S(2)
);

U3: fulladder port map (
    A => A(3),
    B => B(3),
    Cin => CR(2),
    Cout=> CR(3),
    S => S(3)
);

END structural;

------------------------------------------------------

-- This is testbench design:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY rca4_tb IS
END rca4_tb;

ARCHITECTURE test OF rca4_tb IS

component rca4
Port ( A, B: in std_logic_vector(3 downto 0);
       Cin: in std_logic;
       Cout: out std_logic;
       S: out std_logic_vector(3 downto 0));
END component;

signal A, B, S: STD_LOGIC_VECTOR(3 downto 0);
signal Cin, Cout : STD_LOGIC;

BEGIN

G1: rca4 port map (
    A => A,
    B => B,
    Cin => Cin,
    Cout=> Cout,
    S => S
);

Process
Begin
   A <="0110";
   B <="1001";
   Cin <= '0';
   Wait for 10 ns;
   A <="0111";
   B <="0010";
   Cin <= '1';
   Wait for 10 ns;
   A <="0111";
   B <="0101";
   Cin <= '1';
   Wait for 10 ns;
   Wait;

End process;


END test;