LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;


ENTITY shiftreg IS
PORT
(
  Din, clk, clr : IN STD_LOGIC;
  Q : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END shiftreg;

ARCHITECTURE beh OF shiftreg IS
signal W: std_logic_vector(3 downto 0);

BEGIN

process( clk, clr )
begin
  if (clr = '1') then
     W <= "0000";
  elsif (rising_edge (clk)) then
     W(3) <= Din;
     W(2) <= W(3);
     W(1) <= W(2);
     W(0) <= W(1);
  end if;
end process;

Q <= W;


END beh;

-----------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY shiftreg_tb is
End shiftreg_tb;
ARCHITECTURE beh OF shiftreg_tb IS

Component shiftreg
PORT ( 
  Din, clk, clr : IN STD_LOGIC;
  Q : OUT STD_LOGIC_VECTOR(3 downto 0) );
END Component;

signal Din, clk, clr: std_logic;
signal Q: std_logic_vector(3 downto 0);

BEGIN

uut: shiftreg port map( Din=>Din, clk=>clk, clr=>clr, Q=>Q);

Process
Begin
  Clk <= '0'; Wait for 10 ns;
  Clk <= '1'; Wait for 10 ns;
End process;


Process
Begin
   Din <='0'; clr<='1';
   Wait for 12 ns;
   Din <='1'; clr<='0';
   Wait for 40 ns;
   Din <= '0';
   Wait;
End process;

END beh;