LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY lfsr IS
PORT
(
reset, clk: IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(4 downto 1)
);
END lfsr;
ARCHITECTURE beh OF lfsr IS
signal W: std_logic_vector(4 downto 1);
BEGIN
process( clk, reset )
begin
if (reset='1') then
W <= ( 1=>'1', others => '0' );
elsif (rising_edge (clk)) then
W <= W(3 downto 2) & ( W(1) xor W(4) ) & W(4);
end if;
end process;
Q <= W;
END beh;

--------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY lfsr_tb is
End lfsr_tb;

ARCHITECTURE beh OF lfsr_tb IS

Component lfsr
PORT
(
   reset, clk: IN STD_LOGIC;
   Q : OUT STD_LOGIC_VECTOR(4 downto 1)
);
END Component;

signal reset, clk: std_logic;
signal Q: std_logic_vector(4 downto 1);

BEGIN

uut: lfsr port map( reset=>reset, clk=>clk, Q=>Q);

Process
Begin
  Clk <= '0';
  Wait for 10 ns;
  Clk <= '1';
  Wait for 10 ns;
End process;


Process
Begin
  reset <='1';
  Wait for 6 ns;
  reset <='0';
  Wait for 40 ns;
  Wait;
End process;

END beh;