Syntax:
SIGNAL_NAME <= value_expr_1 when boolean_expr_1 
               else value_expr_2 when boolean_expr_2 
               else value_expr_3 when boolean_expr_3 
               else 
               . . . 
               value_expr_n; 

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LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
 
ENTITY examplewhenelse IS 
       PORT ( input0, input1, sel   : IN STD_LOGIC; 
              output : OUT STD_LOGIC ); 
END examplewhenelse; 
 
ARCHITECTURE choice OF examplewhenelse IS 
BEGIN 
     
     output <= input0 WHEN sel = '0' ELSE input1; 
 
END choice; 

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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; 
 
ENTITY examplewhenelse_tb IS 
END examplewhenelse_tb; 
 
ARCHITECTURE beh OF examplewhenelse_tb IS 

    component examplewhenelse 
    PORT ( input0, input1, sel  : IN STD_LOGIC; 
           output : OUT STD_LOGIC ); 
    end component; 
 
signal input0, input1, sel  : STD_LOGIC; signal output: STD_LOGIC; 
 
BEGIN 

      uut: examplewhenelse  port map ( input0 => input0, input1 => input1, sel => sel, output => output ); 
 
     input0 <= '0', '1' after 20 ns, '0' after 40 ns; 
     input1 <= '0', '1' after 10 ns, '0' after 20 ns , '0' after 30 ns, '1' after 40 ns; 
     sel    <= '0', '1' after 30 ns; 
 
END beh; 


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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; 
 
ENTITY givencircuit IS 
   PORT ( A, B,C,D   : IN STD_LOGIC; 
         SEL:   IN STD_LOGIC_VECTOR(1 downto 0); 
         DOUT : OUT STD_LOGIC ); 
END givencircuit; 
   
ARCHITECTURE design OF givencircuit IS BEGIN 
 
   DOUT  <=       A WHEN SEL =  "00" 
             ELSE B WHEN SEL =  "01" 
             ELSE C WHEN SEL =  "10" 
             ELSE D; 
 
END design;