library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity fsm_v3 is

port ( clk, reset : IN std_logic;
       y : OUT std_logic );

end fsm_v3;

architecture beh of fsm_v3 is

type state_type is (idle,s1,s2,s3, s4);

signal state: state_type ;

signal count : STD_LOGIC_VECTOR(3 downto 0);
begin


process (clk,reset)
begin
if (reset ='1') then
   count <= "0000";
   y     <= '0';
   state <= idle;

elsif ( rising_edge(clk) ) then

  case state is

  when idle =>  state <= s1;
                count <= "0000";
                y     <= '0';

  when s1 =>
 
        count <= count + 1;
        if (count = 8) then
          state <= s2;          
        else
          state <= s1;
        end if;
        y <= '0';

  when s2 => state <= s3;
             y <= '1';
             

  when s3 => state <= s4;
             count <= "0000";
             y <= '0';

  when s4 => count <= count + 1;
           if (count = 5) then
              state <= s1;
              count <= "0000";
           else
              state <= s4;
           end if;
           
           y <= '0';
            

  when others => state <= s1;
                 count <= "0000";
                 y     <= '0';
  end case;

end if;

end process;



end beh;