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LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
 
ENTITY mux4 IS 
       PORT ( a, b, c, d   : IN STD_LOGIC; 
              s: IN STD_LOGIC_VECTOR (1 downto 0);
              y: OUT STD_LOGIC ); 
END mux4; 
 
ARCHITECTURE sel_arch OF mux4 IS 
BEGIN 
     with s select
     y <= a WHEN "00",
          b WHEN "01",
          c WHEN "10"
          d WHEN others;
 
END sel_arch; 

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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; 
 
ENTITY mux_tb IS 
END mux_tb; 
 
ARCHITECTURE beh OF mux_tb IS 

    component mux
    PORT ( a, b, c, d   : IN STD_LOGIC; 
              s: IN STD_LOGIC_VECTOR (1 downto 0);
              y: OUT STD_LOGIC ); 
    end component; 
 
signal a,b,c,d  : STD_LOGIC; 
signal sel:       STD_LOGIC_VECTOR(1 downto 0);
signal y:         STD_LOGIC; 
 
BEGIN 
      uut: mux
      port map ( a,b,c,d,sel, y ); 
 
     a <= '0', '1' after 80 ns, '0' after 160 ns, '1' after 200 ns; 
     b <= ... ;
     c <= ... ;
     d <= ... ;

     sel<= "00", "01" after 40 ns, "10" after 70 ns , "11" after 170 ns; 
    
 
END beh;