Dr. Pang's CPE 166 Page
Week-----Mo--Tu--We--Th--Fr
Jan 01   21  22  23  24  25
    02   28  29  30  31  Feb 1  
Feb 03    4   5   6   7  8
    04   11  12  13  14  15
    05   18  19  20  21  22
    06   25  26  27  28  Mar 1 
Mar 07    4   5   6   7  8
    08   11  12  13  14  15
    -    18  19  20  21  22   [ spring recess ]
    09    25  26  27  28  29 
Apr 10    1   2   3   4  5
    11    8   9  10  11  12
    12   15  16  17  18  19
    13   22  23  24  25  26
    14   29  30   1   2  3
May 15    6   7   8   9  10
Fin 16   13  14  15  16  17

    

    test_xor.v , displayed results
    More:
     mycir circuit, mycir.v & mycir_tb.v, displayed results
     dec2to4 circuit, dec2to4.v & dec2to4_tb.v, displayed results

     Exercise 1:  full adder solution 
     Exercise 2: dec3_8   (p59 ). 
     Exercise 3: dec4_16 (p59 - p61).
     

      ha.v & ha_tb.v, displayed results
     
      fa.v & fa_tb.v, displayed results
      rca3 circuit, rca3.v & rca3_tb.v, displayed results


     *******************************************************
     *     JPG1 ,  JPG2 ,  JPG3 ,  JPG4     *
     *******************************************************  


      mux2to1.v & mux2to1_tb.v, displayed results

     *******************************************************
     *     FPGA Pins    *
     *******************************************************


    Lab2 - Part 1 
     L2-Part 1 Project           	  
    
     dff_e1.v & dff_e1_tb.v,  dff_e2.v & dff_e2_tb.v,  dff_e3.v & dff_e3_tb.v, 
     Moore FSM,  Mearly FSM, mealy
     dffb.v & dffb_tb.v
       
     fpga_fun.txt, Pins        
   
    
     myand.vhd, myand_tb.vhd 
     mycir.vhd, mycir_tb.vhd 

 
     mycounter, bcd  
     down_counter, clkdiv8   
    display counter      

     rca4
     dff, shiftreg,      

    whenelse      

    moore     mealy 
    fsm_v3
    
    lfsr-fig     lfsr 
    lfsr-fig2     lfsr2 

    when ... else  
    with ... select  




     ASM Charts  


     *******************************************************
     *    Error Detection & Correction   *
     *******************************************************
      Even/Odd Parity    
      Verilog Parity    
      VHDL Parity    
     (7,4) Hamming Code   
     (7,4) Hamming Code Diagram   
     Modulo 2 Arithmetic   
     CRC Error Detection   
     (2)  

      SRAM Handout
      ram 
     (2)

      mem_fsm 
      mem_top 
      metastability 
      hazard 
      Dice Game  ( 2 ) 

     Final Exam Schedule:  Wed., May 15, 10:15 am - 12:15 pm